Many computer devices operate based on an external clock. For example, a processor may receive a clock input and perform all operations or events only when the clock transitions. Devices in which events proceed based on a clock transition are referred to as "synchronous" devices.
Other computer devices do not base their operation on an external clock. These devices are referred to as "asynchronous" or "self-timed" devices. A memory array such as that contained in a cache subsystem is one example of a device that can be implemented as a self-timed device. A self-timed memory array typically receives a request from a processor (e.g., a read or write request). The memory array then performs the operation and indicates to the processor when the operation is complete. However, the time required for the operation to complete is not based on an external clock (i.e., a predetermined number of clock cycles). Rather, in the case of a self-timed cache subsystem, the time required is based on the asynchronous delay paths through the device, which may vary in duration based on the operations that are performed.
Self-timed devices typically have some performance advantages over synchronous devices. Specifically, self-timed devices have a lower speed power product than similar synchronous devices. A speed power product is the speed of the device multiplied by the power consumed by the device at a given frequency. With self-timed devices, power is only consumed during operations. In contrast, with synchronous devices, power is consumed by clock distribution buffers even when operations are not being performed.
Synchronous devices frequently are required to interact with self-timed devices. When a synchronous device interacts with self-timed memory arrays, there is a need for an input interface that receives input signals from the synchronous device.
Specifically, the device containing the self-timed memory array needs to accept input signals using the clock-based protocol of the synchronous device. For example, a synchronous device will typically drive valid data for a window of time around a clock edge or edges as defined by setup time (i.e., a valid time before a clock edge) and hold time (i.e., a valid time after a clock edge) specifications. The self-timed device, however, may need input data for a duration of time that is different (e.g., longer) than the synchronous time provides. Thus, a synchronous interface is needed to convert the input signals to a protocol that is compatible with the self-timed memory array timing requirements.
The interface must make the self-timed memory array appear to be a synchronous device to other devices. For maximum performance, the interface should also reduce input/output signal delay, and minimize the input signal setup time and hold time requirements.
Based on the foregoing, there is a need for such a synchronous interface to a self-timed memory array.